[PATCH] D104236: [AArch64] Add a TableGen pattern to generate uaddlv from uaddlp and addv

JinGu Kang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 5 04:39:29 PDT 2021

Previous message: [PATCH] D104236: [AArch64] Add a TableGen pattern to generate uaddlv from uaddlp and addv
Next message: [PATCH] D113160: [stack-safety] Check SCEV constraints at memory instructions.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

jaykang10 added a comment.

I have create a new review https://reviews.llvm.org/D113263.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104236/new/

https://reviews.llvm.org/D104236

Previous message: [PATCH] D104236: [AArch64] Add a TableGen pattern to generate uaddlv from uaddlp and addv
Next message: [PATCH] D113160: [stack-safety] Check SCEV constraints at memory instructions.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list