[PATCH] D113212: [DAGCombiner] add fold for vselect of signbit

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks! I've added an additional testcase for MVE in rGcb62c3761fe7 <https://reviews.llvm.org/rGcb62c3761fe709d9e180c0d341c8658a290c53bf>. (Which is less instructions but may technically be slower now that I think about it - depending on if the vmov is loop invariant and how the microachitecture handles overlap. You can ignore that though - I just wanted to make sure there were some tests for an architecture with first class vector predicates, and any performance gains/losses should be minor and dependent a lot on the surrounding code. They are less instructions in the general case).



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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9555
+
+  SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1);
+  ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
----------------
I find it easier to read with one definition per line.


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  https://reviews.llvm.org/D113212/new/

https://reviews.llvm.org/D113212