[PATCH] D113178: [PowerPC] use right register class for input operand of XXPERMDIs

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:1069
   let isCodeGenOnly = 1 in
-  def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
+  def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsrc:$XA, u2imm:$DM),
                              "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
----------------
shchenz wrote:
> jsji wrote:
> > I believe the intention was to use `XXPERMDIs` for single precision , for `vsfrc`, while `XXPERMDI` for `vsrc`.
> > Are we sure we are using `XXPERMDIs` correctly in D106555?
> ```
>   def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
>                              "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
> ```
> 
> `XXPERMDIs` should be an operation based on doubleword. I think the suffix `s` is for same, which means register operand are both the same?
> 
> Compared with `XXPERMDI`:
> ```
>   def XXPERMDI : XX3Form_2<60, 10,
>                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
>                        "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm,
>                        [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
>                          imm32SExt16:$DM))]>;
> ```
> 
> `VSFRC` is for `f64`, `VSSRC` is for `f32`, `vsrc` is for a vector type?
Yes:

- `F8RC` contains first 64 `double`
- `VFRC` contains second 64 `double`
- `VSLRC` contains first 64 `vector`
- `VRRC` contains second 64 `vector`
- `VSSRC` contains all 128 `float`
- `VSFRC` contains all 128 `double`
- `VSRC` contains all 128 `vector`


Repository:
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  https://reviews.llvm.org/D113178/new/

https://reviews.llvm.org/D113178