[PATCH] D113212: [DAGCombiner] add fold for vselect of signbit

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: dmgreen, RKSimon, craig.topper.
Herald added subscribers: ecnelises, pengfei, hiraditya, kristof.beyls, mcrosier.
spatel requested review of this revision.
Herald added a project: LLVM.

(X s< 0) ? Y : 0 --> (X s>> BW-1) & Y

We canonicalize to the icmp+select form in IR, and we already have this fold for scalar select in SDAG, so I think it's an oversight that we don't have the fold for vectors. It seems neutral for AArch64 and saves some instructions on x86.

Whether we should also have the sibling folds for the inverse condition or all-ones true value may depend on target-specific factors such as whether there's an "and-not" instruction.


https://reviews.llvm.org/D113212

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/vselect-constants.ll
  llvm/test/CodeGen/X86/avx512-logic.ll
  llvm/test/CodeGen/X86/avx512vl-logic.ll
  llvm/test/CodeGen/X86/vselect-zero.ll

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