[PATCH] D113193: [TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB

[Guozhi Wei via Phabricator via llvm-commits]

Carrot created this revision.
Carrot added reviewers: craig.topper, pengfei, RKSimon, stoklund.
Herald added subscribers: mstorsjo, hiraditya.
Carrot requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Currently we create register mappings for registers used only once in current MBB. For registers with multiple uses, when all the uses are in the current MBB, we can also create mappings for them similarly according to the last use. For example

  %reg101 = ...
                  = ... reg101
  %reg103 = ADD %reg101, %reg102

We can create mapping between %reg101 and %reg103.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113193

Files:
  llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
  llvm/test/CodeGen/ARM/ssat.ll
  llvm/test/CodeGen/ARM/usat.ll
  llvm/test/CodeGen/SystemZ/int-div-01.ll
  llvm/test/CodeGen/SystemZ/int-div-03.ll
  llvm/test/CodeGen/SystemZ/int-div-04.ll
  llvm/test/CodeGen/SystemZ/int-mul-08.ll
  llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
  llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
  llvm/test/CodeGen/X86/atomic-unordered.ll
  llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
  llvm/test/CodeGen/X86/bitreverse.ll
  llvm/test/CodeGen/X86/bmi2.ll
  llvm/test/CodeGen/X86/bypass-slow-division-32.ll
  llvm/test/CodeGen/X86/combine-bitselect.ll
  llvm/test/CodeGen/X86/combine-sdiv.ll
  llvm/test/CodeGen/X86/ctpop-combine.ll
  llvm/test/CodeGen/X86/divide-by-constant.ll
  llvm/test/CodeGen/X86/fshr.ll
  llvm/test/CodeGen/X86/haddsub-3.ll
  llvm/test/CodeGen/X86/haddsub-shuf.ll
  llvm/test/CodeGen/X86/haddsub.ll
  llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll
  llvm/test/CodeGen/X86/horizontal-sum.ll
  llvm/test/CodeGen/X86/lzcnt-cmp.ll
  llvm/test/CodeGen/X86/nontemporal-loads.ll
  llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
  llvm/test/CodeGen/X86/pmulh.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/pull-binop-through-shift.ll
  llvm/test/CodeGen/X86/rem.ll
  llvm/test/CodeGen/X86/sat-add.ll
  llvm/test/CodeGen/X86/sdiv_fix_sat.ll
  llvm/test/CodeGen/X86/setcc-combine.ll
  llvm/test/CodeGen/X86/shift-combine.ll
  llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
  llvm/test/CodeGen/X86/slow-pmulld.ll
  llvm/test/CodeGen/X86/smul_fix.ll
  llvm/test/CodeGen/X86/smul_fix_sat.ll
  llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/X86/sse3-avx-addsub-2.ll
  llvm/test/CodeGen/X86/uadd_sat.ll
  llvm/test/CodeGen/X86/uadd_sat_vec.ll
  llvm/test/CodeGen/X86/umul-with-overflow.ll
  llvm/test/CodeGen/X86/umul_fix.ll
  llvm/test/CodeGen/X86/umul_fix_sat.ll
  llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/X86/vec-strict-cmp-128.ll
  llvm/test/CodeGen/X86/vec_ctbits.ll
  llvm/test/CodeGen/X86/vec_umulo.ll
  llvm/test/CodeGen/X86/vector-bitreverse.ll
  llvm/test/CodeGen/X86/vector-ext-logic.ll
  llvm/test/CodeGen/X86/vector-fshl-128.ll
  llvm/test/CodeGen/X86/vector-fshr-128.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
  llvm/test/CodeGen/X86/vector-lzcnt-128.ll
  llvm/test/CodeGen/X86/vector-lzcnt-sub128.ll
  llvm/test/CodeGen/X86/vector-narrow-binop.ll
  llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
  llvm/test/CodeGen/X86/vector-popcnt-128.ll
  llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll
  llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
  llvm/test/CodeGen/X86/vector-trunc-packus.ll
  llvm/test/CodeGen/X86/vector-trunc-ssat.ll
  llvm/test/CodeGen/X86/vector-trunc-usat.ll
  llvm/test/CodeGen/X86/vector-tzcnt-128.ll
  llvm/test/CodeGen/X86/vselect-packss.ll

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