[PATCH] D113178: [PowerPC] use right register class for XXPERMDIs

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
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This is from code review comments for D106555 <https://reviews.llvm.org/D106555>

In D106555 <https://reviews.llvm.org/D106555>, after we added:

  def : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)),
            (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>;
  def : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)),
            (v2i64 (XXPERMDIs (LFIWAX ForceXForm:$A), 0))>;

some LIT cases change the input for vector splat instruction from `vs0` to `f0`. But for vector splat instruction, like `xxspltd`, `vs0` makes more sense than `f0`.

This patch changes register class for `XXPERMDIs` from `vsfrc` to `vsrc`. Now `XXPERMDIs` has same input type with `XXPERMDI`. So that it needs a vector register instead of a scalar float register.

Some other vector instructions have same issue, like `XXSLDWI`/`XXSLDWIs`, `XXSPLTW`/`XXSPLTWs`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D113178

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/build-vector-tests.ll
  llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
  llvm/test/CodeGen/PowerPC/load-and-splat.ll
  llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll

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