[PATCH] D113150: Lift VLIWResourceModel, VLIWMachineScheduler, and ConvergingVLIWScheduler into CodeGen/VLIWMachineScheduler
James Nagurne via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 3 15:37:53 PDT 2021
JamesNagurne created this revision.
JamesNagurne added a reviewer: kparzysz.
JamesNagurne added a project: LLVM.
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The Pre-RA VLIWMachineScheduler used by Hexagon is a relatively generic
implementation that would make sense to use on other VLIW targets.
This commit lifts those classes into their own header/source file with the
root VLIWMachineScheduler. I chose this path rather than adding the
strategy et al. into MachineScheduler to avoid bloating the file with other
implementations.
Target-specific behaviors have been captured and replicated through
function overloads.
- Created an overloadable DFAPacketizer creation member function so
that other targets are not restricted to the Packetizer created for the
subtarget.
- Added an extra helper which returns the number of instructions in the
current packet.
- Placed the priority heuristic values into the ConvergingVLIWscheduler
class instead of them being local statics in the implementation
- Added a overridable helper in ConvergingVLIWScheduler so that targets
can create their own VLIWResourceModel
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D113150
Files:
llvm/include/llvm/CodeGen/VLIWMachineScheduler.h
llvm/lib/CodeGen/CMakeLists.txt
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/VLIWMachineScheduler.cpp
llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
llvm/lib/Target/Hexagon/HexagonMachineScheduler.h
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
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