[llvm] 4bef030 - [AArch64, AMDGPU] Use make_early_inc_range (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 3 09:23:02 PDT 2021
Author: Kazu Hirata
Date: 2021-11-03T09:22:51-07:00
New Revision: 4bef0304e153c757c9f42c2001d4c56e8f99929e
URL: https://github.com/llvm/llvm-project/commit/4bef0304e153c757c9f42c2001d4c56e8f99929e
DIFF: https://github.com/llvm/llvm-project/commit/4bef0304e153c757c9f42c2001d4c56e8f99929e.diff
LOG: [AArch64, AMDGPU] Use make_early_inc_range (NFC)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp b/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
index c996d2df8c38..cd67e058a9c1 100644
--- a/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
@@ -377,8 +377,7 @@ void AArch64AdvSIMDScalar::transformInstruction(MachineInstr &MI) {
// processMachineBasicBlock - Main optimzation loop.
bool AArch64AdvSIMDScalar::processMachineBasicBlock(MachineBasicBlock *MBB) {
bool Changed = false;
- for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
- MachineInstr &MI = *I++;
+ for (MachineInstr &MI : llvm::make_early_inc_range(*MBB)) {
if (isProfitableToTransform(MI)) {
transformInstruction(MI);
Changed = true;
diff --git a/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp b/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
index 5d8af760f5ac..d2488f61eb4b 100644
--- a/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
+++ b/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
@@ -176,20 +176,19 @@ bool AArch64StackTaggingPreRA::mayUseUncheckedLoadStore() {
}
void AArch64StackTaggingPreRA::uncheckUsesOf(unsigned TaggedReg, int FI) {
- for (auto UI = MRI->use_instr_begin(TaggedReg), E = MRI->use_instr_end();
- UI != E;) {
- MachineInstr *UseI = &*(UI++);
- if (isUncheckedLoadOrStoreOpcode(UseI->getOpcode())) {
+ for (MachineInstr &UseI :
+ llvm::make_early_inc_range(MRI->use_instructions(TaggedReg))) {
+ if (isUncheckedLoadOrStoreOpcode(UseI.getOpcode())) {
// FI operand is always the one before the immediate offset.
- unsigned OpIdx = TII->getLoadStoreImmIdx(UseI->getOpcode()) - 1;
- if (UseI->getOperand(OpIdx).isReg() &&
- UseI->getOperand(OpIdx).getReg() == TaggedReg) {
- UseI->getOperand(OpIdx).ChangeToFrameIndex(FI);
- UseI->getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED);
+ unsigned OpIdx = TII->getLoadStoreImmIdx(UseI.getOpcode()) - 1;
+ if (UseI.getOperand(OpIdx).isReg() &&
+ UseI.getOperand(OpIdx).getReg() == TaggedReg) {
+ UseI.getOperand(OpIdx).ChangeToFrameIndex(FI);
+ UseI.getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED);
}
- } else if (UseI->isCopy() &&
- Register::isVirtualRegister(UseI->getOperand(0).getReg())) {
- uncheckUsesOf(UseI->getOperand(0).getReg(), FI);
+ } else if (UseI.isCopy() &&
+ Register::isVirtualRegister(UseI.getOperand(0).getReg())) {
+ uncheckUsesOf(UseI.getOperand(0).getReg(), FI);
}
}
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
index 4971b010870d..9e86bd0c2b97 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
@@ -95,10 +95,8 @@ bool AMDGPULateCodeGenPrepare::runOnFunction(Function &F) {
bool Changed = false;
for (auto &BB : F)
- for (auto BI = BB.begin(), BE = BB.end(); BI != BE; /*EMPTY*/) {
- Instruction *I = &*BI++;
- Changed |= visit(*I);
- }
+ for (Instruction &I : llvm::make_early_inc_range(BB))
+ Changed |= visit(I);
return Changed;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
index 714e74faaf13..b700dd5aa301 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
@@ -76,9 +76,8 @@ bool AMDGPULowerIntrinsics::expandMemIntrinsicUses(Function &F) {
Intrinsic::ID ID = F.getIntrinsicID();
bool Changed = false;
- for (auto I = F.user_begin(), E = F.user_end(); I != E;) {
- Instruction *Inst = cast<Instruction>(*I);
- ++I;
+ for (User *U : llvm::make_early_inc_range(F.users())) {
+ Instruction *Inst = cast<Instruction>(U);
switch (ID) {
case Intrinsic::memcpy: {
diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
index 2bf365168048..a8c85ec4e5ea 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -612,8 +612,7 @@ bool GCNDPPCombine::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
for (auto &MBB : MF) {
- for (auto I = MBB.rbegin(), E = MBB.rend(); I != E;) {
- auto &MI = *I++;
+ for (MachineInstr &MI : llvm::make_early_inc_range(llvm::reverse(MBB))) {
if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) {
Changed = true;
++NumDPPMovsCombined;
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 3ec82fe48a24..eab3ae47f15a 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -1157,11 +1157,7 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
bool SeenDbgInstr = false;
for (MachineBasicBlock &MBB : MF) {
- MachineBasicBlock::iterator Next;
- for (auto I = MBB.begin(), E = MBB.end(); I != E; I = Next) {
- MachineInstr &MI = *I;
- Next = std::next(I);
-
+ for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
if (MI.isDebugInstr())
SeenDbgInstr = true;
diff --git a/llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp b/llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
index d560b477b8ba..4fa8ec711134 100644
--- a/llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
@@ -140,11 +140,7 @@ bool SILateBranchLowering::runOnMachineFunction(MachineFunction &MF) {
bool MadeChange = false;
for (MachineBasicBlock &MBB : MF) {
- MachineBasicBlock::iterator I, Next;
- for (I = MBB.begin(); I != MBB.end(); I = Next) {
- Next = std::next(I);
- MachineInstr &MI = *I;
-
+ for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
switch (MI.getOpcode()) {
case AMDGPU::S_BRANCH:
// Optimize out branches to the next block.
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 193d106a1230..fee3b7028de2 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -332,11 +332,7 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
BitVector SpillFIs(MFI.getObjectIndexEnd(), false);
for (MachineBasicBlock &MBB : MF) {
- MachineBasicBlock::iterator Next;
- for (auto I = MBB.begin(), E = MBB.end(); I != E; I = Next) {
- MachineInstr &MI = *I;
- Next = std::next(I);
-
+ for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
if (!TII->isSGPRSpill(MI))
continue;
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