[PATCH] D104156: [DAGCombine][X86][ARM] EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(?,?,Mask)) -> VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(?, ?), EXTRACT_SUBVECTOR(?, ?), Mask')

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 384403.
lebedev.ri marked 3 inline comments as done.
lebedev.ri added a comment.

@RKSimon thank you for taking a look!
Addressed some nits.

In D104156#3105627 <https://reviews.llvm.org/D104156#3105627>, @RKSimon wrote:

> Do we have any test coverage with any subvectors that are not half the width of the source? 512-bit -> 128-bit AVX512 shuffles for instance.

I've checked and it doesn't appear so.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104156/new/

https://reviews.llvm.org/D104156

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll
  llvm/test/CodeGen/ARM/vext.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
  llvm/test/CodeGen/X86/vector-rotate-256.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
  llvm/test/CodeGen/X86/vector-shift-shl-256.ll
  llvm/test/CodeGen/X86/vector-trunc.ll

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