[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

Wed Nov 3 00:47:50 PDT 2021

fzhinkin added a comment.

In D111530#3104217 <https://reviews.llvm.org/D111530#3104217>, @lebedev.ri wrote:

> In D111530#3104196 <https://reviews.llvm.org/D111530#3104196>, @fzhinkin wrote:
>
>> In D111530#3104045 <https://reviews.llvm.org/D111530#3104045>, @lebedev.ri wrote:
>>
>>> X86 changes look good. Are AArch64 changes actually a regressions, or are they just changes?
>>
>> Thanks!
>> There  is no regression for AArch64: better code sequence is generated for legalized `i128` shifts, but there is no improvement for wider types (like `i256`).
>
> A change that only triggers for some (common?) cases and causes no regressions is a better step forward
> than a change that indiscriminately triggers on everything and causes widespread regressions i would think :)

I agree. I don't think that i256 and wider types are something frequently you can see in real code.

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https://reviews.llvm.org/D111530