[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

[Filipp Zhinkin via Phabricator via llvm-commits]

fzhinkin added a comment.

In D111530#3104045 <https://reviews.llvm.org/D111530#3104045>, @lebedev.ri wrote:

> X86 changes look good. Are AArch64 changes actually a regressions, or are they just changes?

Thanks!
There  is no regression for AArch64: better code sequence is generated for legalized `i128` shifts, but there is no improvement for wider types (like `i256`).


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  https://reviews.llvm.org/D111530/new/

https://reviews.llvm.org/D111530