[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

Tue Nov 2 13:31:27 PDT 2021

fzhinkin added a comment.

In D111530#3102654 <https://reviews.llvm.org/D111530#3102654>, @RKSimon wrote:

> In D111530#3101173 <https://reviews.llvm.org/D111530#3101173>, @RKSimon wrote:
>
>> In D111530#3100864 <https://reviews.llvm.org/D111530#3100864>, @fzhinkin wrote:
>>
>>> Instead I supported funnel shifts `TargetLowering::optimizeSetCCOfExpandedShift` (did not support rotations and bit/byte swaps because such nodes should not be created during expanded shift's combining).
>>>
>>> While optimization works fine for i686 now there is an issue with AArch64: shifts expanded from types wider than `i128` won't be optimized (see `@opt_setcc_shl_ne_zero_i256`) because for AArch64 funnel shift alike patterns combined into `AArch64ISD::EXTR` instead of FSHL/FSHR. I attempted to fix it by implementing (2), but the solution was fragile and didn't work in some cases.
>>
>> I'm hoping D112443 <https://reviews.llvm.org/D112443> will help with this
>
> D112443 <https://reviews.llvm.org/D112443> has been committed - please can you see if it helps?

Unfortunately it didn't affect AArch64ISD::EXTR combining.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111530/new/

https://reviews.llvm.org/D111530