[PATCH] D113005: [AMDGPU] Fix subreg checks in S_MOV_B64_IMM_PSEUDO generation.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp:96-97
+  //
+  // Note: It's tricky to do this in the next def_instructions() loop since the
+  // AMDGPU::COPY handling there can potentially modify the IR. TODO: Can we
+  // move the AGPR copy optimization somewhere else?
----------------
Can you just change the range loop to preincrement the iterator?


================
Comment at: llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp:102-116
+      if (Opc == AMDGPU::COPY || Opc == AMDGPU::S_MOV_B32) {
+        switch (I.getOperand(0).getSubReg()) {
+        default:
+          return false;
+
+        case AMDGPU::sub0:
+          ++NumDef0;
----------------
Checking for specific opcodes with specific subreg indices is definitely not the right way to check for register interference.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113005/new/

https://reviews.llvm.org/D113005