[llvm] fce5a56 - [AMDGPU] More robust checks in extract_vector_dynelt.ll

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-11-02T13:26:31Z
New Revision: fce5a567c64f26b2df8d99e228bb6cb6acd0da92

URL: https://github.com/llvm/llvm-project/commit/fce5a567c64f26b2df8d99e228bb6cb6acd0da92
DIFF: https://github.com/llvm/llvm-project/commit/fce5a567c64f26b2df8d99e228bb6cb6acd0da92.diff

LOG: [AMDGPU] More robust checks in extract_vector_dynelt.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
index 50a505d5e14ba..b66ab4e577aaf 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
@@ -234,7 +234,7 @@ entry:
 ; GCN-LABEL: {{^}}double8_extelt:
 ; GCN-NOT: buffer_
 ; GCN-NOT: s_or_b32
-; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
+; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}}
 ; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
 ; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
 ; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]
@@ -250,7 +250,7 @@ entry:
 ; GCN-LABEL: {{^}}double7_extelt:
 ; GCN-NOT: buffer_
 ; GCN-NOT: s_or_b32
-; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
+; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}}
 ; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
 ; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
 ; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]
@@ -294,7 +294,7 @@ entry:
 ; GCN-LABEL: {{^}}double15_extelt:
 ; GCN-NOT: buffer_
 ; GCN-NOT: s_or_b32
-; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
+; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}}
 ; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
 ; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
 ; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]
@@ -310,7 +310,7 @@ entry:
 ; GCN-LABEL: {{^}}double16_extelt:
 ; GCN-NOT: buffer_
 ; GCN-NOT: s_or_b32
-; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
+; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0{{$}}
 ; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
 ; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
 ; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]