[PATCH] D112911: Fix the side effect of outlined function when register is implicit and implicit-def

[DianQK via Phabricator via llvm-commits]

DianQK updated this revision to Diff 384041.
DianQK added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112911/new/

https://reviews.llvm.org/D112911

Files:
  llvm/lib/CodeGen/MachineOutliner.cpp
  llvm/test/CodeGen/AArch64/machine-outliner-side-effect-2.mir
  llvm/test/CodeGen/AArch64/machine-outliner-side-effect.mir


Index: llvm/test/CodeGen/AArch64/machine-outliner-side-effect.mir
===================================================================
--- llvm/test/CodeGen/AArch64/machine-outliner-side-effect.mir
+++ llvm/test/CodeGen/AArch64/machine-outliner-side-effect.mir
@@ -29,4 +29,4 @@
 
 ...
 
-# CHECK: BL @OUTLINED_FUNCTION_0, {{.*}}, implicit $x20, {{.*}}
+# CHECK: BL @OUTLINED_FUNCTION_0, {{.*}}, implicit $x20{{.*}}
Index: llvm/test/CodeGen/AArch64/machine-outliner-side-effect-2.mir
===================================================================
--- llvm/test/CodeGen/AArch64/machine-outliner-side-effect-2.mir
+++ llvm/test/CodeGen/AArch64/machine-outliner-side-effect-2.mir
@@ -16,7 +16,8 @@
     liveins: $x0, $lr
 
     $x1 = ADDXri $sp, 16, 0
-    BL @spam, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit-def $sp, implicit-def dead $x0
+    BL @spam, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit-def $sp, implicit-def $x0
+    renamable $x1 = COPY $x0
 
     RET_ReallyLR
 
@@ -29,7 +30,8 @@
     liveins: $x0, $lr
 
     $x1 = ADDXri $sp, 16, 0
-    BL @spam, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit-def $sp, implicit-def dead $x0
+    BL @spam, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit-def $sp, implicit-def $x0
+    renamable $x2 = COPY $x0
 
     RET_ReallyLR
 
@@ -42,10 +44,11 @@
     liveins: $x0, $lr
 
     $x1 = ADDXri $sp, 16, 0
-    BL @spam, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit-def $sp, implicit-def dead $x0
+    BL @spam, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit killed $x1, implicit-def $sp, implicit-def $x0
+    renamable $x3 = COPY $x0
 
     RET_ReallyLR
 
 ...
 
-# CHECK: BL @OUTLINED_FUNCTION_0, {{.*}}, implicit $x0
+# CHECK: BL @OUTLINED_FUNCTION_0, {{.*}}, implicit $x0{{.*}}
Index: llvm/lib/CodeGen/MachineOutliner.cpp
===================================================================
--- llvm/lib/CodeGen/MachineOutliner.cpp
+++ llvm/lib/CodeGen/MachineOutliner.cpp
@@ -798,6 +798,7 @@
                  Last = std::next(CallInst.getReverse());
              Iter != Last; Iter++) {
           MachineInstr *MI = &*Iter;
+          SmallSet<Register, 2> InstrUseRegs;
           for (MachineOperand &MOP : MI->operands()) {
             // Skip over anything that isn't a register.
             if (!MOP.isReg())
@@ -806,7 +807,8 @@
             if (MOP.isDef()) {
               // Introduce DefRegs set to skip the redundant register.
               DefRegs.insert(MOP.getReg());
-              if (!MOP.isDead() && UseRegs.count(MOP.getReg()))
+              if (UseRegs.count(MOP.getReg()) &&
+                  !InstrUseRegs.count(MOP.getReg()))
                 // Since the regiester is modeled as defined,
                 // it is not necessary to be put in use register set.
                 UseRegs.erase(MOP.getReg());
@@ -814,6 +816,7 @@
               // Any register which is not undefined should
               // be put in the use register set.
               UseRegs.insert(MOP.getReg());
+              InstrUseRegs.insert(MOP.getReg());
             }
           }
           if (MI->isCandidateForCallSiteEntry())


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