[llvm] a9a8952 - [RISCV][test] Precommit tests for D108129.
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 1 19:38:10 PDT 2021
Author: jacquesguan
Date: 2021-11-02T02:29:47Z
New Revision: a9a895207f854be212819a0202799e1fcd118cc0
URL: https://github.com/llvm/llvm-project/commit/a9a895207f854be212819a0202799e1fcd118cc0
DIFF: https://github.com/llvm/llvm-project/commit/a9a895207f854be212819a0202799e1fcd118cc0.diff
LOG: [RISCV][test] Precommit tests for D108129.
Reviewed By: frasercrmck, RKSimon
Differential Revision: https://reviews.llvm.org/D110675
Added:
llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
Modified:
llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
index 340694828c416..dd25bbc4c9cbc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
@@ -24,3 +24,327 @@ define <vscale x 4 x i1> @srem_eq_fold_nxv4i8(<vscale x 4 x i8> %va) {
%cc = icmp eq <vscale x 4 x i8> %rem, zeroinitializer
ret <vscale x 4 x i1> %cc
}
+
+define <vscale x 1 x i32> @vmulh_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vmulh_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vmulh.vv v8, v9, v8
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %ve = mul <vscale x 1 x i64> %vc, %vd
+ %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vf = lshr <vscale x 1 x i64> %ve, %splat
+ %vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %vg
+}
+
+define <vscale x 1 x i32> @vmulh_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulh_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 1 x i32> undef, i32 %x, i32 0
+ %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+ %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = mul <vscale x 1 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %ve = lshr <vscale x 1 x i64> %vd, %splat2
+ %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 1 x i32> @vmulh_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: addi a0, zero, -7
+; CHECK-NEXT: vmul.vx v8, v9, a0
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v8, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
+ %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+ %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = mul <vscale x 1 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %ve = lshr <vscale x 1 x i64> %vd, %splat2
+ %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 1 x i32> @vmulh_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv1i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vsext.vf2 v9, v8
+; CHECK-NEXT: vsll.vi v8, v9, 4
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v8, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+ %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+ %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = mul <vscale x 1 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %ve = lshr <vscale x 1 x i64> %vd, %splat2
+ %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulh_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vmulh_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmulh.vv v8, v9, v8
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %ve = mul <vscale x 2 x i64> %vc, %vd
+ %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vf = lshr <vscale x 2 x i64> %ve, %splat
+ %vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %vg
+}
+
+define <vscale x 2 x i32> @vmulh_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulh_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 2 x i32> undef, i32 %x, i32 0
+ %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+ %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = mul <vscale x 2 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %ve = lshr <vscale x 2 x i64> %vd, %splat2
+ %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulh_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: addi a0, zero, -7
+; CHECK-NEXT: vmul.vx v8, v10, a0
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v10, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
+ %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+ %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = mul <vscale x 2 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %ve = lshr <vscale x 2 x i64> %vd, %splat2
+ %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulh_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv2i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vsext.vf2 v10, v8
+; CHECK-NEXT: vsll.vi v8, v10, 4
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v10, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+ %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+ %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = mul <vscale x 2 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %ve = lshr <vscale x 2 x i64> %vd, %splat2
+ %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulh_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vmulh_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmulh.vv v8, v10, v8
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %ve = mul <vscale x 4 x i64> %vc, %vd
+ %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vf = lshr <vscale x 4 x i64> %ve, %splat
+ %vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %vg
+}
+
+define <vscale x 4 x i32> @vmulh_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulh_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 4 x i32> undef, i32 %x, i32 0
+ %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+ %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = mul <vscale x 4 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %ve = lshr <vscale x 4 x i64> %vd, %splat2
+ %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulh_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: addi a0, zero, -7
+; CHECK-NEXT: vmul.vx v8, v12, a0
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v12, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
+ %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+ %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = mul <vscale x 4 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %ve = lshr <vscale x 4 x i64> %vd, %splat2
+ %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulh_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv4i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vsext.vf2 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 4
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v12, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+ %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+ %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = mul <vscale x 4 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %ve = lshr <vscale x 4 x i64> %vd, %splat2
+ %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulh_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vmulh_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vmulh.vv v8, v12, v8
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %ve = mul <vscale x 8 x i64> %vc, %vd
+ %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vf = lshr <vscale x 8 x i64> %ve, %splat
+ %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %vg
+}
+
+define <vscale x 8 x i32> @vmulh_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulh_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> undef, i32 %x, i32 0
+ %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+ %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = mul <vscale x 8 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %ve = lshr <vscale x 8 x i64> %vd, %splat2
+ %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulh_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vsext.vf2 v16, v8
+; CHECK-NEXT: addi a0, zero, -7
+; CHECK-NEXT: vmul.vx v8, v16, a0
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v16, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
+ %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+ %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = mul <vscale x 8 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %ve = lshr <vscale x 8 x i64> %vd, %splat2
+ %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulh_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv8i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vsext.vf2 v16, v8
+; CHECK-NEXT: vsll.vi v8, v16, 4
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v16, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+ %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+ %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = mul <vscale x 8 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %ve = lshr <vscale x 8 x i64> %vd, %splat2
+ %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %vf
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
new file mode 100644
index 0000000000000..b2cfd5b78576e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
@@ -0,0 +1,411 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+
+define <vscale x 1 x i32> @vmulhu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vmulhu_vv_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vmulhu.vv v8, v9, v8
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %ve = mul <vscale x 1 x i64> %vc, %vd
+ %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vf = lshr <vscale x 1 x i64> %ve, %splat
+ %vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %vg
+}
+
+define <vscale x 1 x i32> @vmulhu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulhu_vx_nxv1i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 1 x i32> undef, i32 %x, i32 0
+ %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+ %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = mul <vscale x 1 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %ve = lshr <vscale x 1 x i64> %vd, %splat2
+ %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; RV32-LABEL: vmulhu_vi_nxv1i32_0:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: addi a0, zero, -7
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vzext.vf2 v10, v8
+; RV32-NEXT: vmul.vv v8, v10, v9
+; RV32-NEXT: addi a0, zero, 32
+; RV32-NEXT: vsrl.vx v8, v8, a0
+; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; RV32-NEXT: vnsrl.wi v8, v8, 0
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vmulhu_vi_nxv1i32_0:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; RV64-NEXT: vzext.vf2 v9, v8
+; RV64-NEXT: addi a0, zero, 1
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: vmul.vx v8, v9, a0
+; RV64-NEXT: addi a0, zero, 32
+; RV64-NEXT: vsrl.vx v8, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; RV64-NEXT: vnsrl.wi v8, v8, 0
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
+ %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+ %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = mul <vscale x 1 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %ve = lshr <vscale x 1 x i64> %vd, %splat2
+ %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv1i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vzext.vf2 v9, v8
+; CHECK-NEXT: vsll.vi v8, v9, 4
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v8, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+ %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+ %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+ %vd = mul <vscale x 1 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %ve = lshr <vscale x 1 x i64> %vd, %splat2
+ %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulhu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vmulhu_vv_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmulhu.vv v8, v9, v8
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %ve = mul <vscale x 2 x i64> %vc, %vd
+ %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vf = lshr <vscale x 2 x i64> %ve, %splat
+ %vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %vg
+}
+
+define <vscale x 2 x i32> @vmulhu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulhu_vx_nxv2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 2 x i32> undef, i32 %x, i32 0
+ %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+ %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = mul <vscale x 2 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %ve = lshr <vscale x 2 x i64> %vd, %splat2
+ %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; RV32-LABEL: vmulhu_vi_nxv2i32_0:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: addi a0, zero, -7
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vzext.vf2 v12, v8
+; RV32-NEXT: vmul.vv v8, v12, v10
+; RV32-NEXT: addi a0, zero, 32
+; RV32-NEXT: vsrl.vx v10, v8, a0
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; RV32-NEXT: vnsrl.wi v8, v10, 0
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vmulhu_vi_nxv2i32_0:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; RV64-NEXT: vzext.vf2 v10, v8
+; RV64-NEXT: addi a0, zero, 1
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: vmul.vx v8, v10, a0
+; RV64-NEXT: addi a0, zero, 32
+; RV64-NEXT: vsrl.vx v10, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT: vnsrl.wi v8, v10, 0
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
+ %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+ %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = mul <vscale x 2 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %ve = lshr <vscale x 2 x i64> %vd, %splat2
+ %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv2i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vsll.vi v8, v10, 4
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v10, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v10, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+ %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+ %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+ %vd = mul <vscale x 2 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %ve = lshr <vscale x 2 x i64> %vd, %splat2
+ %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulhu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vmulhu_vv_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmulhu.vv v8, v10, v8
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %ve = mul <vscale x 4 x i64> %vc, %vd
+ %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vf = lshr <vscale x 4 x i64> %ve, %splat
+ %vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %vg
+}
+
+define <vscale x 4 x i32> @vmulhu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulhu_vx_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 4 x i32> undef, i32 %x, i32 0
+ %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+ %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = mul <vscale x 4 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %ve = lshr <vscale x 4 x i64> %vd, %splat2
+ %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; RV32-LABEL: vmulhu_vi_nxv4i32_0:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: addi a0, zero, -7
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vzext.vf2 v16, v8
+; RV32-NEXT: vmul.vv v8, v16, v12
+; RV32-NEXT: addi a0, zero, 32
+; RV32-NEXT: vsrl.vx v12, v8, a0
+; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV32-NEXT: vnsrl.wi v8, v12, 0
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vmulhu_vi_nxv4i32_0:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; RV64-NEXT: vzext.vf2 v12, v8
+; RV64-NEXT: addi a0, zero, 1
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: vmul.vx v8, v12, a0
+; RV64-NEXT: addi a0, zero, 32
+; RV64-NEXT: vsrl.vx v12, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64-NEXT: vnsrl.wi v8, v12, 0
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
+ %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+ %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = mul <vscale x 4 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %ve = lshr <vscale x 4 x i64> %vd, %splat2
+ %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv4i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vsll.vi v8, v12, 4
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v12, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v12, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+ %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+ %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+ %vd = mul <vscale x 4 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %ve = lshr <vscale x 4 x i64> %vd, %splat2
+ %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulhu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vmulhu_vv_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vmulhu.vv v8, v12, v8
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %ve = mul <vscale x 8 x i64> %vc, %vd
+ %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vf = lshr <vscale x 8 x i64> %ve, %splat
+ %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %vg
+}
+
+define <vscale x 8 x i32> @vmulhu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulhu_vx_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vmulhu.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> undef, i32 %x, i32 0
+ %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+ %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = mul <vscale x 8 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %ve = lshr <vscale x 8 x i64> %vd, %splat2
+ %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; RV32-LABEL: vmulhu_vi_nxv8i32_0:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: addi a0, zero, -7
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vzext.vf2 v24, v8
+; RV32-NEXT: vmul.vv v8, v24, v16
+; RV32-NEXT: addi a0, zero, 32
+; RV32-NEXT: vsrl.vx v16, v8, a0
+; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; RV32-NEXT: vnsrl.wi v8, v16, 0
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vmulhu_vi_nxv8i32_0:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV64-NEXT: vzext.vf2 v16, v8
+; RV64-NEXT: addi a0, zero, 1
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: vmul.vx v8, v16, a0
+; RV64-NEXT: addi a0, zero, 32
+; RV64-NEXT: vsrl.vx v16, v8, a0
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; RV64-NEXT: vnsrl.wi v8, v16, 0
+; RV64-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
+ %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+ %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = mul <vscale x 8 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %ve = lshr <vscale x 8 x i64> %vd, %splat2
+ %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv8i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vzext.vf2 v16, v8
+; CHECK-NEXT: vsll.vi v8, v16, 4
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v16, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsrl.wi v8, v16, 0
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+ %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+ %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+ %vd = mul <vscale x 8 x i64> %vb, %vc
+ %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+ %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %ve = lshr <vscale x 8 x i64> %vd, %splat2
+ %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %vf
+}
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