[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D111530#3100864 <https://reviews.llvm.org/D111530#3100864>, @fzhinkin wrote:

> Instead I supported funnel shifts `TargetLowering::optimizeSetCCOfExpandedShift` (did not support rotations and bit/byte swaps because such nodes should not be created during expanded shift's combining).
>
> While optimization works fine for i686 now there is an issue with AArch64: shifts expanded from types wider than `i128` won't be optimized (see `@opt_setcc_shl_ne_zero_i256`) because for AArch64 funnel shift alike patterns combined into `AArch64ISD::EXTR` instead of FSHL/FSHR. I attempted to fix it by implementing (2), but the solution was fragile and didn't work in some cases.

I'm hoping D112443 <https://reviews.llvm.org/D112443> will help with this


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https://reviews.llvm.org/D111530