[llvm] bd932f7 - [NFC][PowerPC] Update testcases using script
Jinsong Ji via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 1 08:37:58 PDT 2021
Author: Jinsong Ji
Date: 2021-11-01T15:37:23Z
New Revision: bd932f7499ff7ab958f5bc2f55dcf4b06cd87950
URL: https://github.com/llvm/llvm-project/commit/bd932f7499ff7ab958f5bc2f55dcf4b06cd87950
DIFF: https://github.com/llvm/llvm-project/commit/bd932f7499ff7ab958f5bc2f55dcf4b06cd87950.diff
LOG: [NFC][PowerPC] Update testcases using script
For D106555.
Added:
Modified:
llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
index f4572c359942..77d0116c1b7d 100644
--- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
@@ -14,24 +15,27 @@ define <2 x i64> @s2v_test1(i32* nocapture readonly %int32, <2 x i64> %vec) {
; P9LE-NEXT: lfiwax f0, 0, r3
; P9LE-NEXT: xxmrghd v2, v2, vs0
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test1:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfiwax f0, 0, r3
; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test1:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfiwax f0, 0, r3
; P8LE-NEXT: xxmrghd v2, v2, vs0
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test1:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfiwax f0, 0, r3
; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
; P8BE-NEXT: blr
+
+
+
entry:
%0 = load i32, i32* %int32, align 4
%conv = sext i32 %0 to i64
@@ -47,27 +51,30 @@ define <2 x i64> @s2v_test2(i32* nocapture readonly %int32, <2 x i64> %vec) {
; P9LE-NEXT: lfiwax f0, 0, r3
; P9LE-NEXT: xxmrghd v2, v2, vs0
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test2:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addi r3, r3, 4
; P9BE-NEXT: lfiwax f0, 0, r3
; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test2:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: lfiwax f0, 0, r3
; P8LE-NEXT: xxmrghd v2, v2, vs0
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test2:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addi r3, r3, 4
; P8BE-NEXT: lfiwax f0, 0, r3
; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
; P8BE-NEXT: blr
+
+
+
entry:
%arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
%0 = load i32, i32* %arrayidx, align 4
@@ -84,27 +91,30 @@ define <2 x i64> @s2v_test3(i32* nocapture readonly %int32, <2 x i64> %vec, i32
; P9LE-NEXT: lfiwax f0, r3, r4
; P9LE-NEXT: xxmrghd v2, v2, vs0
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test3:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: sldi r4, r7, 2
; P9BE-NEXT: lfiwax f0, r3, r4
; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test3:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r7, 2
; P8LE-NEXT: lfiwax f0, r3, r4
; P8LE-NEXT: xxmrghd v2, v2, vs0
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test3:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: sldi r4, r7, 2
; P8BE-NEXT: lfiwax f0, r3, r4
; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
; P8BE-NEXT: blr
+
+
+
entry:
%idxprom = sext i32 %Idx to i64
%arrayidx = getelementptr inbounds i32, i32* %int32, i64 %idxprom
@@ -122,27 +132,30 @@ define <2 x i64> @s2v_test4(i32* nocapture readonly %int32, <2 x i64> %vec) {
; P9LE-NEXT: lfiwax f0, 0, r3
; P9LE-NEXT: xxmrghd v2, v2, vs0
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test4:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addi r3, r3, 4
; P9BE-NEXT: lfiwax f0, 0, r3
; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test4:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: addi r3, r3, 4
; P8LE-NEXT: lfiwax f0, 0, r3
; P8LE-NEXT: xxmrghd v2, v2, vs0
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test4:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addi r3, r3, 4
; P8BE-NEXT: lfiwax f0, 0, r3
; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
; P8BE-NEXT: blr
+
+
+
entry:
%arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
%0 = load i32, i32* %arrayidx, align 4
@@ -158,24 +171,27 @@ define <2 x i64> @s2v_test5(<2 x i64> %vec, i32* nocapture readonly %ptr1) {
; P9LE-NEXT: lfiwax f0, 0, r5
; P9LE-NEXT: xxmrghd v2, v2, vs0
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test5:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfiwax f0, 0, r5
; P9BE-NEXT: xxpermdi v2, vs0, v2, 1
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test5:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfiwax f0, 0, r5
; P8LE-NEXT: xxmrghd v2, v2, vs0
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test5:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfiwax f0, 0, r5
; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
; P8BE-NEXT: blr
+
+
+
entry:
%0 = load i32, i32* %ptr1, align 4
%conv = sext i32 %0 to i64
@@ -190,24 +206,27 @@ define <2 x i64> @s2v_test6(i32* nocapture readonly %ptr) {
; P9LE-NEXT: lfiwax f0, 0, r3
; P9LE-NEXT: xxspltd v2, vs0, 0
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test6:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfiwax f0, 0, r3
; P9BE-NEXT: xxspltd v2, vs0, 0
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test6:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfiwax f0, 0, r3
; P8LE-NEXT: xxspltd v2, vs0, 0
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test6:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfiwax f0, 0, r3
; P8BE-NEXT: xxspltd v2, vs0, 0
; P8BE-NEXT: blr
+
+
+
entry:
%0 = load i32, i32* %ptr, align 4
%conv = sext i32 %0 to i64
@@ -223,24 +242,27 @@ define <2 x i64> @s2v_test7(i32* nocapture readonly %ptr) {
; P9LE-NEXT: lfiwax f0, 0, r3
; P9LE-NEXT: xxspltd v2, vs0, 0
; P9LE-NEXT: blr
-
+;
; P9BE-LABEL: s2v_test7:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfiwax f0, 0, r3
; P9BE-NEXT: xxspltd v2, vs0, 0
; P9BE-NEXT: blr
-
+;
; P8LE-LABEL: s2v_test7:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfiwax f0, 0, r3
; P8LE-NEXT: xxspltd v2, vs0, 0
; P8LE-NEXT: blr
-
+;
; P8BE-LABEL: s2v_test7:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfiwax f0, 0, r3
; P8BE-NEXT: xxspltd v2, vs0, 0
; P8BE-NEXT: blr
+
+
+
entry:
%0 = load i32, i32* %ptr, align 4
%conv = sext i32 %0 to i64
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