[llvm] 7afef22 - [AMDGPU] Use MachineInstrBuilder::addReg. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 1 08:31:19 PDT 2021
Author: Jay Foad
Date: 2021-11-01T15:29:51Z
New Revision: 7afef22926113effa0b8dbdcb59da579198a7b62
URL: https://github.com/llvm/llvm-project/commit/7afef22926113effa0b8dbdcb59da579198a7b62
DIFF: https://github.com/llvm/llvm-project/commit/7afef22926113effa0b8dbdcb59da579198a7b62.diff
LOG: [AMDGPU] Use MachineInstrBuilder::addReg. NFC.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 776326896cf0..e201dab74c77 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5199,8 +5199,7 @@ void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,
return;
Register DstReg = MRI.createVirtualRegister(DstRC);
- MachineInstr *Copy =
- BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).add(Op);
+ auto Copy = BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).add(Op);
Op.setReg(DstReg);
Op.setSubReg(0);
@@ -5222,7 +5221,7 @@ void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,
}
if (!RI.isSGPRClass(DstRC) && !Copy->readsRegister(AMDGPU::EXEC, &RI) &&
!ImpDef)
- Copy->addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
+ Copy.addReg(AMDGPU::EXEC, RegState::Implicit);
}
// Emit the actual waterfall loop, executing the wrapped instruction for each
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