[PATCH] D108129: [DAGCombiner] Teach combineShiftToMULH to handle constant and const splat vector.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8562
 
-  if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode())
+  if (!(IsSignExt || IsZeroExt))
     return SDValue();
----------------
craig.topper wrote:
> Can you re-write this to
> 
> `if (!IsSignExt && !ZeroExt)`
> 
> 
Done


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll:3
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+
----------------
craig.topper wrote:
> One of these RUN lines should be -mtriple=riscv64
Done.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108129/new/

https://reviews.llvm.org/D108129