[PATCH] D108129: [DAGCombiner] Teach combineShiftToMULH to handle constant and const splat vector.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8562
 
-  if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode())
+  if (!(IsSignExt || IsZeroExt))
     return SDValue();
----------------
Can you re-write this to

`if (!IsSignExt && !ZeroExt)`




Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108129/new/

https://reviews.llvm.org/D108129