[PATCH] D109300: [AMDGPU] Make vector superclasses allocatable

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas updated this revision to Diff 383645.
cdevadas added a comment.

Removed the workaround post-Selection that forced a Vreg class for the occurrences of AV classes. With D112323 <https://reviews.llvm.org/D112323>, we no longer choose AV superclasses during instruction selection. They either become a Vreg class or an Areg class.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109300/new/

https://reviews.llvm.org/D109300

Files:
  llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll

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