[llvm] 5dd9e01 - [AArch64][GlobalISel] Fix an crash in RBS due to a new regclass being added.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-10-29T11:47:00-07:00
New Revision: 5dd9e019ddb4b3e1d9fe425ae8bfe5a01b3f66fa

URL: https://github.com/llvm/llvm-project/commit/5dd9e019ddb4b3e1d9fe425ae8bfe5a01b3f66fa
DIFF: https://github.com/llvm/llvm-project/commit/5dd9e019ddb4b3e1d9fe425ae8bfe5a01b3f66fa.diff

LOG: [AArch64][GlobalISel] Fix an crash in RBS due to a new regclass being added.

rdar://84674985

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 5af0b2d9e202b..40ddf6a94f734 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -13,6 +13,8 @@
 
 #include "AArch64RegisterBankInfo.h"
 #include "AArch64InstrInfo.h"
+#include "AArch64RegisterInfo.h"
+#include "MCTargetDesc/AArch64MCTargetDesc.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
@@ -272,6 +274,7 @@ AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
   case AArch64::WSeqPairsClassRegClassID:
   case AArch64::XSeqPairsClassRegClassID:
   case AArch64::MatrixIndexGPR32_12_15RegClassID:
+  case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID:
     return getRegBank(AArch64::GPRRegBankID);
   case AArch64::CCRRegClassID:
     return getRegBank(AArch64::CCRegBankID);

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
new file mode 100644
index 0000000000000..2da63a82a7ca1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/rbs-matrixindex-regclass-crash.mir
@@ -0,0 +1,56 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+# Check we don't crash because of an unhandled new regclass GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID.
+---
+name:            foo
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: foo
+    ; CHECK: [[DEF:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: $x0 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x1 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x2 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x3 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x4 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x5 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x6 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x7 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x8 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x9 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x10 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x11 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x12 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x13 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x14 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x15 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x16 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: $x17 = COPY [[DEF]](s64)
+    ; CHECK-NEXT: INLINEASM &"svc 0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $x0, 10 /* regdef */, implicit-def $x1, 10 /* regdef */, implicit-def $x2, 10 /* regdef */, implicit-def $x3, 10 /* regdef */, implicit-def $x4, 10 /* regdef */, implicit-def $x5, 10 /* regdef */, implicit-def $x6, 10 /* regdef */, implicit-def $x7, 10 /* regdef */, implicit-def $x8, 10 /* regdef */, implicit-def $x9, 10 /* regdef */, implicit-def $x10, 10 /* regdef */, implicit-def $x11, 10 /* regdef */, implicit-def $x12, 10 /* regdef */, implicit-def $x13, 10 /* regdef */, implicit-def $x14, 10 /* regdef */, implicit-def $x15, 10 /* regdef */, implicit-def $x16, 10 /* regdef */, implicit-def $x17, 9 /* reguse */, $x0, 9 /* reguse */, $x1, 9 /* reguse */, $x2, 9 /* reguse */, $x3, 9 /* reguse */, $x4, 9 /* reguse */, $x5, 9 /* reguse */, $x6, 9 /* reguse */, $x7, 9 /* reguse */, $x8, 9 /* reguse */, $x9, 9 /* reguse */, $x10, 9 /* reguse */, $x11, 9 /* reguse */, $x12, 9 /* reguse */, $x13, 9 /* reguse */, $x14, 9 /* reguse */, $x15, 9 /* reguse */, $x16, 9 /* reguse */, $x17
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:_(s64) = G_IMPLICIT_DEF
+    $x0 = COPY %0(s64)
+    $x1 = COPY %0(s64)
+    $x2 = COPY %0(s64)
+    $x3 = COPY %0(s64)
+    $x4 = COPY %0(s64)
+    $x5 = COPY %0(s64)
+    $x6 = COPY %0(s64)
+    $x7 = COPY %0(s64)
+    $x8 = COPY %0(s64)
+    $x9 = COPY %0(s64)
+    $x10 = COPY %0(s64)
+    $x11 = COPY %0(s64)
+    $x12 = COPY %0(s64)
+    $x13 = COPY %0(s64)
+    $x14 = COPY %0(s64)
+    $x15 = COPY %0(s64)
+    $x16 = COPY %0(s64)
+    $x17 = COPY %0(s64)
+    INLINEASM &"svc 0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $x0, 10 /* regdef */, implicit-def $x1, 10 /* regdef */, implicit-def $x2, 10 /* regdef */, implicit-def $x3, 10 /* regdef */, implicit-def $x4, 10 /* regdef */, implicit-def $x5, 10 /* regdef */, implicit-def $x6, 10 /* regdef */, implicit-def $x7, 10 /* regdef */, implicit-def $x8, 10 /* regdef */, implicit-def $x9, 10 /* regdef */, implicit-def $x10, 10 /* regdef */, implicit-def $x11, 10 /* regdef */, implicit-def $x12, 10 /* regdef */, implicit-def $x13, 10 /* regdef */, implicit-def $x14, 10 /* regdef */, implicit-def $x15, 10 /* regdef */, implicit-def $x16, 10 /* regdef */, implicit-def $x17, 9 /* reguse */, $x0, 9 /* reguse */, $x1, 9 /* reguse */, $x2, 9 /* reguse */, $x3, 9 /* reguse */, $x4, 9 /* reguse */, $x5, 9 /* reguse */, $x6, 9 /* reguse */, $x7, 9 /* reguse */, $x8, 9 /* reguse */, $x9, 9 /* reguse */, $x10, 9 /* reguse */, $x11, 9 /* reguse */, $x12, 9 /* reguse */, $x13, 9 /* reguse */, $x14, 9 /* reguse */, $x15, 9 /* reguse */, $x16, 9 /* reguse */, $x17
+    RET_ReallyLR
+
+...