[llvm] 52fc2ed - AMDGPU: Check kernarg alignments in test
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 29 09:42:41 PDT 2021
Author: Matt Arsenault
Date: 2021-10-29T12:42:36-04:00
New Revision: 52fc2edb5357075c7c746adc274d513f48d412b8
URL: https://github.com/llvm/llvm-project/commit/52fc2edb5357075c7c746adc274d513f48d412b8
DIFF: https://github.com/llvm/llvm-project/commit/52fc2edb5357075c7c746adc274d513f48d412b8.diff
LOG: AMDGPU: Check kernarg alignments in test
Strangely the kernel code object header clamps the value to a minimum
of 16, but the emitted metadata only clamps to a minimum of 4.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
index aefc91762793..7431832fa7d7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
@@ -4,15 +4,35 @@
; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
; HSA: enable_sgpr_kernarg_segment_ptr = 0
; HSA: kernarg_segment_byte_size = 0
+; HSA: kernarg_segment_alignment = 4
; MESA: enable_sgpr_kernarg_segment_ptr = 1
; MESA: kernarg_segment_byte_size = 16
+; MESA: kernarg_segment_alignment = 4
+
+; HSA: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0{{$}}
+; HSA: s_load_dword s0, [[NULL]], 0x0
+define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
+ %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
+ %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+ %load = load volatile i32, i32 addrspace(4)* %cast
+ ret void
+}
+
+; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty_0implicit:
+; HSA: enable_sgpr_kernarg_segment_ptr = 0
+; HSA: kernarg_segment_byte_size = 0
+; HSA: kernarg_segment_alignment = 4
+
+; MESA: enable_sgpr_kernarg_segment_ptr = 1
+; MESA: kernarg_segment_byte_size = 16
+; MESA: kernarg_segment_alignment = 4
; HSA: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0{{$}}
; HSA: s_load_dword s0, [[NULL]], 0x0
; MESA: s_load_dword s0, s[4:5], 0x0
-define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
+define amdgpu_kernel void @kernel_implicitarg_ptr_empty_0implicit() #3 {
%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
%load = load volatile i32, i32 addrspace(4)* %cast
@@ -23,7 +43,10 @@ define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA: kernarg_segment_byte_size = 48
+; HSA: kernarg_segment_alignment = 4
+
; MESA: kernarg_segment_byte_size = 16
+; MESA: kernarg_segment_alignment = 4
; HSA: s_load_dword s0, s[4:5], 0x0
define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {
@@ -37,7 +60,10 @@ define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {
; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA: kernarg_segment_byte_size = 112
+; HSA: kernarg_segment_alignment = 4
+
; MESA: kernarg_segment_byte_size = 128
+; MESA: kernarg_segment_alignment = 4
; HSA: s_load_dword s0, s[4:5], 0x1c
define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
@@ -51,7 +77,10 @@ define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA: kernarg_segment_byte_size = 160
+; HSA: kernarg_segment_alignment = 4
+
; MESA: kernarg_segment_byte_size = 128
+; MESA: kernarg_segment_alignment = 4
; HSA: s_load_dword s0, s[4:5], 0x1c
define amdgpu_kernel void @opencl_kernel_implicitarg_ptr([112 x i8]) #1 {
@@ -88,16 +117,36 @@ define void @opencl_func_implicitarg_ptr() #0 {
; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:
; HSA: enable_sgpr_kernarg_segment_ptr = 0
; HSA: kernarg_segment_byte_size = 0
+; HSA: kernarg_segment_alignment = 4
; MESA: enable_sgpr_kernarg_segment_ptr = 1
; MESA: kernarg_segment_byte_size = 16
+; MESA: kernarg_segment_alignment = 4
+
+; XGCN-NOT: s[4:5]
+; XGCN-NOT: s4
+; XGCN-NOT: s5
+; GCN: s_swappc_b64
+define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {
+ call void @func_implicitarg_ptr()
+ ret void
+}
+
+; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty_implicit0:
+; HSA: enable_sgpr_kernarg_segment_ptr = 0
+; HSA: kernarg_segment_byte_size = 0
+; HSA: kernarg_segment_alignment = 4
+
+; MESA: enable_sgpr_kernarg_segment_ptr = 1
+; MESA: kernarg_segment_byte_size = 16
+; MESA: kernarg_segment_alignment = 4
; HSA: s_mov_b64 s[4:5], 0{{$}}
; MESA-NOT: s[4:5]
; MESA-NOT: s4
; MESA-NOT: s5
; GCN: s_swappc_b64
-define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {
+define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty_implicit0() #3 {
call void @func_implicitarg_ptr()
ret void
}
@@ -105,7 +154,9 @@ define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {
; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty:
; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA: kernarg_segment_byte_size = 48
+; HSA: kernarg_segment_alignment = 4
; MESA: kernarg_segment_byte_size = 16
+; MESA: kernarg_segment_alignment = 4
; GCN-NOT: s[4:5]
; GCN-NOT: s4
; GCN-NOT: s5
@@ -118,7 +169,9 @@ define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 {
; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func:
; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA: kernarg_segment_byte_size = 112
+; HSA: kernarg_segment_alignment = 4
; MESA: kernarg_segment_byte_size = 128
+; MESA: kernarg_segment_alignment = 4
; HSA: s_add_u32 s4, s4, 0x70
; MESA: s_add_u32 s4, s4, 0x70
@@ -133,7 +186,9 @@ define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 {
; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func:
; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA: kernarg_segment_byte_size = 160
+; HSA: kernarg_segment_alignment = 4
; MESA: kernarg_segment_byte_size = 128
+; MESA: kernarg_segment_alignment = 4
; GCN: s_add_u32 s4, s4, 0x70
; GCN: s_addc_u32 s5, s5, 0{{$}}
@@ -213,9 +268,61 @@ define amdgpu_kernel void @kernel_implicitarg_no_struct_align_padding(<16 x i32>
ret void
}
+
+; HSA-LABEL: Kernels:
+; HSA-LABEL: - Name: kernel_implicitarg_ptr_empty
+; HSA: CodeProps:
+; HSA: KernargSegmentSize: 0
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: kernel_implicitarg_ptr_empty_0implicit
+; HSA: KernargSegmentSize: 0
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: opencl_kernel_implicitarg_ptr_empty
+; HSA: KernargSegmentSize: 48
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: kernel_implicitarg_ptr
+; HSA: KernargSegmentSize: 112
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: opencl_kernel_implicitarg_ptr
+; HSA: KernargSegmentSize: 160
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: kernel_call_implicitarg_ptr_func_empty
+; HSA: KernargSegmentSize: 0
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: kernel_call_implicitarg_ptr_func_empty_implicit0
+; HSA: KernargSegmentSize: 0
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: opencl_kernel_call_implicitarg_ptr_func_empty
+; HSA: KernargSegmentSize: 48
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: kernel_call_implicitarg_ptr_func
+; HSA: KernargSegmentSize: 112
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: opencl_kernel_call_implicitarg_ptr_func
+; HSA: KernargSegmentSize: 160
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: kernel_call_kernarg_implicitarg_ptr_func
+; HSA: KernargSegmentSize: 112
+; HSA: KernargSegmentAlign: 4
+
+; HSA-LABEL: - Name: kernel_implicitarg_no_struct_align_padding
+; HSA: KernargSegmentSize: 120
+; HSA: KernargSegmentAlign: 64
+
declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #2
declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2
attributes #0 = { nounwind noinline }
attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="48" }
attributes #2 = { nounwind readnone speculatable }
+attributes #3 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="0" }
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