[PATCH] D111519: [WIP] [RISCV] Emit cfi directives for function epilogue

Shivam Gupta via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 28 07:15:33 PDT 2021 

xgupta updated this revision to Diff 383026.
xgupta added a comment.
Herald added subscribers: arphaman, arichardson, MatzeB.
Herald added a reviewer: luke957.

update all test cases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111519/new/

https://reviews.llvm.org/D111519

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll
  llvm/test/CodeGen/RISCV/addimm-mulimm.ll
  llvm/test/CodeGen/RISCV/addrspacecast.ll
  llvm/test/CodeGen/RISCV/aext-to-sext.ll
  llvm/test/CodeGen/RISCV/alu32.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/byval.ll
  llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
  llvm/test/CodeGen/RISCV/calls.ll
  llvm/test/CodeGen/RISCV/copy-frameindex.mir
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/exception-pointer-register.ll
  llvm/test/CodeGen/RISCV/fastcc-int.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/fpenv.ll
  llvm/test/CodeGen/RISCV/frame-info.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll
  llvm/test/CodeGen/RISCV/large-stack.ll
  llvm/test/CodeGen/RISCV/neg-abs.ll
  llvm/test/CodeGen/RISCV/patchable-function-entry.ll
  llvm/test/CodeGen/RISCV/rv32zba.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv32zbs.ll
  llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
  llvm/test/CodeGen/RISCV/rv64zba.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
  llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
  llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
  llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
  llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
  llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
  llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
  llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
  llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
  llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
  llvm/test/CodeGen/RISCV/rvv/load-mask.ll
  llvm/test/CodeGen/RISCV/rvv/localvar.ll
  llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
  llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/select-fp.ll
  llvm/test/CodeGen/RISCV/rvv/select-int.ll
  llvm/test/CodeGen/RISCV/rvv/select-sra.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/stepvector.ll
  llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
  llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpload.ll
  llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vpstore.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
  (62 more files...)

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