[PATCH] D112554: [AMDGPU] Add more llc tests for 48-bit mul generation.

[Abinav Puthan Purayil via Phabricator via llvm-commits]

abinavpp added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll:581-582
+; GCN-NEXT:    v_and_b32_e32 v3, s4, v2
+; GCN-NEXT:    v_mul_u32_u24_e32 v0, v0, v2
+; GCN-NEXT:    v_mul_hi_u32_u24_e32 v1, v1, v3
+; GCN-NEXT:    s_setpc_b64 s[30:31]
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foad wrote:
> This seems to show that we've done a simplify-demanded-bits for the mul (because it is using the original v0 and v2) but not for the mul_hi (which is using the ANDed v1 and v3).
> 
> Maybe AMDGPUTargetLowering::performIntrinsicWOChainCombine needs to call simplifyMul24 for the new mulhi intrinsics?
I missed adding this before. Fix: D112702


Repository:
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  https://reviews.llvm.org/D112554/new/

https://reviews.llvm.org/D112554