[PATCH] D112561: [CodeGen] Don't lower consecutive select instructions with different kind if target don't support it

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

OK. That makes sense. It was just that the test case here we made work already in the backend :) It's not really an unsupported case. It looks like it makes a good testcase though.



================
Comment at: llvm/lib/CodeGen/CodeGenPrepare.cpp:6721
+  // Find all consecutive select instructions that share the same condition and
+  // have same kind.
   SmallVector<SelectInst *, 2> ASI;
----------------
Perhaps change "have the same kind" to "are equally supported"?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112561/new/

https://reviews.llvm.org/D112561