[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

[Hsiangkai Wang via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7051f73d696e: [RISCV] Sync Zvlsseg register order as the same as vector registers. (authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll