[PATCH] D112600: [ARM] Use hardware TLS register in Thumb2 mode when -mtp=cp15 is passed

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers accepted this revision.
nickdesaulniers added a comment.
This revision is now accepted and ready to land.

Cool, if you wouldn't mind additional extending this patch to cover the intrinsic that the front end also generates, this LGTM:

  diff --git a/llvm/test/CodeGen/ARM/thread_pointer.ll b/llvm/test/CodeGen/ARM/thread_pointer.ll
  index c6318a58277c..f1ef2ddac2d0 100644
  --- a/llvm/test/CodeGen/ARM/thread_pointer.ll
  +++ b/llvm/test/CodeGen/ARM/thread_pointer.ll
  @@ -1,4 +1,7 @@
  -; RUN: llc -mtriple arm-linux-gnueabi -filetype asm -o - %s | FileCheck %s
  +; RUN: llc -mtriple arm-linux-gnueabi -o - %s | FileCheck %s -check-prefix=CHECK-SOFT
  +; RUN: llc -mtriple arm-linux-gnueabi -mattr=+read-tp-hard -o - %s | FileCheck %s -check-prefix=CHECK-HARD
  +; RUN: llc -mtriple thumbv7-linux-gnueabi -o - %s | FileCheck %s -check-prefix=CHECK-SOFT
  +; RUN: llc -mtriple thumbv7-linux-gnueabi -mattr=+read-tp-hard -o - %s | FileCheck %s -check-prefix=CHECK-HARD
   
   declare i8* @llvm.thread.pointer()
   
  @@ -8,5 +11,6 @@ entry:
     ret i8* %tmp1
   }
   
  -; CHECK: bl __aeabi_read_tp
  +; CHECK-SOFT: bl __aeabi_read_tp
  +; CHECK-HARD: mrc p15, #0, {{r[0-9]+}}, c13, c0, #3

Thanks for the patch!


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112600/new/

https://reviews.llvm.org/D112600