[PATCH] D112635: [AMDGPU] Disable d16 loads/stores to high halves on gfx90a

[Krzysztof Drewniak via Phabricator via llvm-commits]

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Testing reveals that, on gfx90a, *_load_short_d16_hi does note
preserve the low-order bits of the destination register, even with
SramECC disabled. To prevent the generation of semantically incorrect
code, disable D16PreservesUnesedBits on this target.

(A more specific test may be needed to account for future gfx90*
targets, but checking for gfx90a instructions was what was in the
existing code)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112635

Files:
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/GCNSubtarget.h


Index: llvm/lib/Target/AMDGPU/GCNSubtarget.h
===================================================================
--- llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -591,7 +591,9 @@
   }
 
   bool d16PreservesUnusedBits() const {
-    return hasD16LoadStore() && !TargetID.isSramEccOnOrAny();
+    // gff90a's d16 loads don't preserve unused bits
+    return hasD16LoadStore() && !TargetID.isSramEccOnOrAny() &&
+           !hasGFX90AInsts();
   }
 
   bool hasD16Images() const {
Index: llvm/lib/Target/AMDGPU/AMDGPU.td
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPU.td
+++ llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1343,7 +1343,8 @@
 
 def D16PreservesUnusedBits :
   Predicate<"Subtarget->d16PreservesUnusedBits()">,
-  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
+  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC),
+    (not FeatureGFX90AInsts))>;
 
 def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
 def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;


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