[PATCH] D112599: Fix vm operand constraint to fit GCC's behavior

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng created this revision.
Herald added subscribers: frasercrmck, jdoerfert, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
kito-cheng requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.

- `vm` constraint is used for masking operand, which always v0.

- Update testcase, only masking operand should use `vm`, vector mask operations should just use `vr` for any vector register.
  - Revise the description of `vm` constraint.

- This patch also fix issue on RISCVRegisterInfo.td and RISCVISelLowering.cpp.

  RISCVRegisterInfo.td:
  - The first VT in the list must be the largest total size since the SelectionDAGBuilder uses the first register in the list as the canonical type for the register.

    RISCVISelLowering.cpp:
  - Fix RISCVTargetLowering::splitValueIntoRegisterParts and RISCVTargetLowering::joinRegisterPartsIntoValue for handling vectors with different total size, that will happened on fractional LMUL since fractional LMUL is always occupy one vector register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112599

Files:
  llvm/docs/LangRef.rst
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/inline-asm.ll

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