[PATCH] D112536: [DAG] Add functionality for masked truncating store actions

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Is this needed for SVE support of masked truncating stores? My point in D108115 <https://reviews.llvm.org/D108115> was that we could probably (until someone came along with an opposite position) treat masked truncating stores and truncating stores as symmetric. This will be true for MVE and SVE I think, and is true for X86 as far as I understand. (A second opinion on that would be good though). I imagine RiscV is the same with how their vector architecture works, not sure about hexagon. Sorry for not being very clear on that. Perhaps it's best to add anyway, but the equivalent code for zext/sext masked loads uses isLoadExtLegalOrCustom for the two and hasn't needed to split them into normal/masked variants: https://github.com/llvm/llvm-project/blob/e42f5d4b488e78ebf5b756e1e76422c7458ba81c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L10917

My only comment on D108115 <https://reviews.llvm.org/D108115> was a minor nitpick with formatting and a question about how the AArch64 code was working. RKSimon had a comment about the difficult to update tests too.

On a purely technical note, masked loads/stores only operate on vector types as far as I understand, and TruncMStoreActions doesn't appear to be initialized anywhere.


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  https://reviews.llvm.org/D112536/new/

https://reviews.llvm.org/D112536