[PATCH] D106449: [amdgpu] Handle the case where there is no scavenged register.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:720
   RS->setRegUsed(Scav);
-  return 8;
+  // TODO: The case when there is no scavenged register needs special handling.
+  return;
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Should turn this into an assert


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:721
+  // TODO: The case when there is no scavenged register needs special handling.
+  return;
 }
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Can delete the return


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Comment at: llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=5 -o - %s | FileCheck %s
 
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Can you switch this to an amdhsa triple? I want to be sure the use of the sgpr0_sgpr1 ordinarily used for the scratch buffer is tested. I think you would need to add a test variant that is a non-kernel function too


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D106449/new/

https://reviews.llvm.org/D106449