[PATCH] D112557: [SVE] Fix VLS FMA generation at CodeGenOpt::Aggressive

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Thanks @cameron.mcinally, I see what you mean now.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12572
+  return (OptLevel >= CodeGenOpt::Aggressive) && !VT.isScalableVector() &&
+         !Subtarget->useSVEForFixedLengthVectors();
 }
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Does `!useSVEForFixedLengthVectorVT(VT)` also work? That way we maintain existing behaviour for NEON sized vectors.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll:16
+; RUN: llc -O3 -aarch64-sve-vector-bits-min=1920 < %s | FileCheck %s -D#VBYTES=128
+; RUN: llc -O3 -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -D#VBYTES=256
+
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Given this is a DAG combine I don't see much value in testing all combinations of `-aarch64-sve-vector-bits-min` so perhaps just have a single `RUN` line using the maximum value. That way you don't need `VBYTES` and can use `update_llc_test_checks.py` to generate the `CHECK` lines.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112557/new/

https://reviews.llvm.org/D112557