[PATCH] D112186: [WebAssembly] Add prototype relaxed float to int trunc instructions

[Thomas Lively via Phabricator via llvm-commits]

tlively added inline comments.


================
Comment at: clang/lib/CodeGen/CGBuiltin.cpp:18262-18267
+    case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_trunc_zero_signed;
+      break;
+    case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_trunc_zero_unsigned;
+      break;
----------------
ngzhian wrote:
> @tlively I'm having trouble with this, getting this stack trace
> 
> ```
> WidenVectorResult #0: t4: v2i32 = llvm.wasm.relaxed.trunc.zero.signed TargetConstant:i32<9112>, t2
> 
> Do not know how to widen the result of this operator!
> UNREACHABLE executed at /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3035!
> PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
> Stack dump:
> 0.      Program arguments: /usr/local/google/home/zhin/ssd2/llvm-project/build-wasm/bin/llc -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd -debug
> 1.      Running pass 'Function Pass Manager' on module '<stdin>'.
> 2.      Running pass 'WebAssembly Instruction Selection' on function '@relaxed_trunc_zero_s_v4i32'
>  #0 0x00007f3012db05bb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:565:22
>  #1 0x00007f3012db0672 PrintStackTraceSignalHandler(void*) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:632:1
>  #2 0x00007f3012dae668 llvm::sys::RunSignalHandlers() /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Signals.cpp:97:20
>  #3 0x00007f3012db000e SignalHandler(int) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:407:1
>  #4 0x00007f301276fef0 (/lib/x86_64-linux-gnu/libc.so.6+0x3cef0)
>  #5 0x00007f301276fe71 raise ./signal/../sysdeps/unix/sysv/linux/raise.c:50:1
>  #6 0x00007f3012759536 abort ./stdlib/abort.c:81:7
>  #7 0x00007f3012c5a974 bindingsErrorHandler(void*, char const*, bool) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/ErrorHandling.cpp:218:55
>  #8 0x00007f3016e7856c llvm::DAGTypeLegalizer::WidenVectorResult(llvm::SDNode*, unsigned int) /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3037:71
>  #9 0x00007f3016e4a338 llvm::DAGTypeLegalizer::run() /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:280:17
> #10 0x00007f3016e4e34f llvm::SelectionDAG::LegalizeTypes() /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:1055:37
> ```
> 
> Do I need to add some stuff to LegalizeTypes?
Sorry for the delay in review! The issue is that the code below generates the intrinsic calls with return type <2 x i32>, which is not a legal type, as well as a shuffle to get back to <4 x i32>. For the existing builtins, we use target-independent LLVM intrinsics, so LLVM already knows how to expand them, but it doesn't know how to expand these new target-specific intrinsics. Rather than piggybacking on the  existing logic here, it would be good to generate intrinsics that return the expected <4 x i32> type (and no shuffle) so there is nothing to expand.


Repository:
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  https://reviews.llvm.org/D112186/new/

https://reviews.llvm.org/D112186