[PATCH] D112561: [CodeGen] Don't lower consecutive select instructions with different kind if target don't support it

[Dmitry via Phabricator via llvm-commits]

D.Kharlamov created this revision.
Herald added subscribers: dmgreen, hiraditya.
D.Kharlamov requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112561

Files:
  llvm/lib/CodeGen/CodeGenPrepare.cpp
  llvm/test/CodeGen/Thumb2/mve-selectcc.ll


Index: llvm/test/CodeGen/Thumb2/mve-selectcc.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-selectcc.ll
+++ llvm/test/CodeGen/Thumb2/mve-selectcc.ll
@@ -212,23 +212,24 @@
 ; CHECK-NEXT:    vldrw.u32 q0, [r0]
 ; CHECK-NEXT:    movs r0, #0
 ; CHECK-NEXT:    vmov q2, q0
-; CHECK-NEXT:  .LBB14_1: @ %vector.body
+; CHECK-NEXT:    b .LBB14_2
+; CHECK-NEXT:  .LBB14_1: @ %select.end
+; CHECK-NEXT:    @ in Loop: Header=BB14_2 Depth=1
+; CHECK-NEXT:    vmov q2, q3
+; CHECK-NEXT:  .LBB14_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    adds r0, #4
-; CHECK-NEXT:    vadd.i32 q2, q2, q1
-; CHECK-NEXT:    cmp r0, #8
-; CHECK-NEXT:    cset r1, eq
-; CHECK-NEXT:    cmp r1, #0
-; CHECK-NEXT:    csetm r1, ne
-; CHECK-NEXT:    subs.w r2, r0, #8
-; CHECK-NEXT:    vdup.32 q3, r1
-; CHECK-NEXT:    csel r0, r0, r2, ne
-; CHECK-NEXT:    vbic q2, q2, q3
-; CHECK-NEXT:    vand q3, q3, q0
-; CHECK-NEXT:    vorr q2, q3, q2
+; CHECK-NEXT:    adds r1, r0, #4
+; CHECK-NEXT:    vmov q3, q0
+; CHECK-NEXT:    subs.w r0, r1, #8
+; CHECK-NEXT:    csel r0, r1, r0, ne
+; CHECK-NEXT:    cmp r1, #8
+; CHECK-NEXT:    beq .LBB14_1
+; CHECK-NEXT:  @ %bb.3: @ %select.false
+; CHECK-NEXT:    @ in Loop: Header=BB14_2 Depth=1
+; CHECK-NEXT:    vadd.i32 q3, q2, q1
 ; CHECK-NEXT:    b .LBB14_1
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  @ %bb.2:
+; CHECK-NEXT:  @ %bb.4:
 ; CHECK-NEXT:  .LCPI14_0:
 ; CHECK-NEXT:    .long 0 @ 0x0
 ; CHECK-NEXT:    .long 1 @ 0x1
Index: llvm/lib/CodeGen/CodeGenPrepare.cpp
===================================================================
--- llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -6708,13 +6708,24 @@
   if (DisableSelectToBranch)
     return false;
 
-  // Find all consecutive select instructions that share the same condition.
+  auto GetSelectKind = [](const SelectInst *SI) {
+    if (SI->getCondition()->getType()->isVectorTy())
+      return TargetLowering::VectorMaskSelect;
+    if (SI->getType()->isVectorTy())
+      return TargetLowering::ScalarCondVectorVal;
+    return TargetLowering::ScalarValSelect;
+  };
+
+  bool IsSelectSupported = TLI->isSelectSupported(GetSelectKind(SI));
+  // Find all consecutive select instructions that share the same condition and
+  // have same kind.
   SmallVector<SelectInst *, 2> ASI;
   ASI.push_back(SI);
   for (BasicBlock::iterator It = ++BasicBlock::iterator(SI);
        It != SI->getParent()->end(); ++It) {
     SelectInst *I = dyn_cast<SelectInst>(&*It);
-    if (I && SI->getCondition() == I->getCondition()) {
+    if (I && SI->getCondition() == I->getCondition() &&
+        IsSelectSupported == TLI->isSelectSupported(GetSelectKind(I))) {
       ASI.push_back(I);
     } else {
       break;
@@ -6732,15 +6743,7 @@
   if (VectorCond || SI->getMetadata(LLVMContext::MD_unpredictable))
     return false;
 
-  TargetLowering::SelectSupportKind SelectKind;
-  if (VectorCond)
-    SelectKind = TargetLowering::VectorMaskSelect;
-  else if (SI->getType()->isVectorTy())
-    SelectKind = TargetLowering::ScalarCondVectorVal;
-  else
-    SelectKind = TargetLowering::ScalarValSelect;
-
-  if (TLI->isSelectSupported(SelectKind) &&
+  if (IsSelectSupported &&
       (!isFormingBranchFromSelectProfitable(TTI, TLI, SI) || OptSize ||
        llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI.get())))
     return false;


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