[PATCH] D112557: [SVE] Fix VLS FMA generation at CodeGenOpt::Aggressive

[Cameron McInally via Phabricator via llvm-commits]

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@paulwalker-arm Here is a hastily prepared patch of the problem we discussed earlier today. I'm a little out of the VLS loop, so perhaps there is a better way to handle this...

For VLS lowering, the DAGCombiner is not matching fixed width vector FMAs at CodeGenOpt::Aggressive, since the FMA matching at CodeGenOpt::Aggressive is done in the MachineCombiner. However, when the MachineCombiner runs, we have not yet lowered fixed width vectors to scalable vectors, so FMAs are not generated at all. This patch corrects that by allowing the DAGCombiner to match FMAs if we are using VLS.


https://reviews.llvm.org/D112557

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll

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