[PATCH] D112554: [AMDGPU] Add more llc tests for 48-bit mul generation.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/mul_int24.ll:184-186
+; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v0
+; SI-NEXT:    v_ashr_i64 v[3:4], v[0:1], 40
+; SI-NEXT:    v_ashr_i64 v[1:2], v[1:2], 40
----------------
We should have been able to eliminate these shifts since the high bits are known unused. Maybe we need a SimplifyDemandedBits combine on the mul24/mulhi24 sources?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112554/new/

https://reviews.llvm.org/D112554