[PATCH] D112552: [LoopVectorize] When tail-folding, don't always predicate uniform loads

[David Sherwood via Phabricator via llvm-commits]

david-arm created this revision.
david-arm added reviewers: sdesmalen, kmclaughlin, fhahn, peterwaller-arm.
Herald added subscribers: hiraditya, kristof.beyls.
david-arm requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

In VPRecipeBuilder::handleReplication if we believe the instruction
is predicated we then proceed to create new VP region blocks even
when the load is uniform and only predicated due to tail-folding.
This is unnecessary because we know that if we entered the predicated
vector loop there must be at least one active lane. Therefore, we
can just the treat the load as uniform and unpredicated, and create
a vector splat using the loaded value.

Tests added here:

  Transforms/LoopVectorize/AArch64/tail-fold-uniform-memops.ll


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112552

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/AArch64/tail-fold-uniform-memops.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D112552.382350.patch
Type: text/x-patch
Size: 6378 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20211026/8ef0e0fd/attachment.bin>