[PATCH] D111519: [WIP] [RISCV] Emit cfi directives for function epilogue

[Shivam Gupta via Phabricator via llvm-commits]

xgupta updated this revision to Diff 382276.
xgupta added a comment.
Herald added a subscriber: qcolombet.

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Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111519/new/

https://reviews.llvm.org/D111519

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/test/CodeGen/RISCV/addimm-mulimm.ll
  llvm/test/CodeGen/RISCV/addrspacecast.ll
  llvm/test/CodeGen/RISCV/aext-to-sext.ll
  llvm/test/CodeGen/RISCV/alu32.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/exception-pointer-register.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/fpenv.ll
  llvm/test/CodeGen/RISCV/frame-info.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll
  llvm/test/CodeGen/RISCV/large-stack.ll
  llvm/test/CodeGen/RISCV/neg-abs.ll
  llvm/test/CodeGen/RISCV/patchable-function-entry.ll
  llvm/test/CodeGen/RISCV/rv32zba.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
  llvm/test/CodeGen/RISCV/rv64zba.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
  llvm/test/CodeGen/RISCV/scalable-vector-struct.ll
  llvm/test/CodeGen/RISCV/select-binop-identity.ll
  llvm/test/CodeGen/RISCV/select-constant-xor.ll
  llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
  llvm/test/CodeGen/RISCV/shadowcallstack.ll
  llvm/test/CodeGen/RISCV/shift-and.ll
  llvm/test/CodeGen/RISCV/split-offsets.ll
  llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
  llvm/test/CodeGen/RISCV/stack-realignment.ll
  llvm/test/CodeGen/RISCV/tail-calls.ll
  llvm/test/CodeGen/RISCV/vararg.ll
  llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
  llvm/test/CodeGen/RISCV/xaluo.ll

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