[PATCH] D111888: [AArch64][GISel] Optimize 8 and 16 bit variants of uaddo.
Jessica Paquette via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 25 10:24:00 PDT 2021
paquette added inline comments.
================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp:256
+
+ MachineOperand *DefOp0 = MRI.getOneDef(MI.getOperand(2).getReg());
+ MachineOperand *DefOp1 = MRI.getOneDef(MI.getOperand(3).getReg());
----------------
In this case, you want to match
```
%op0 = G_TRUNC ...
...
%op1 = G_TRUNC ...
%.., %... = G_UADDO %op0, %op1
```
right?
I think you can do
```
if (!mi_match(MI.getOperand(2).getReg(), MRI, m_GTrunc(m_Reg(Op0Wide)) ||
!mi_match(MI.getOperand(3).getReg(), MRI, m_GTrunc(m_Reg(Op1Wide)))
return false;
```
================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp:268
+ LLT OpTy = MRI.getType(ResVal);
+ MachineInstr *Op0WideDef = MRI.getOneDef(Op0Wide)->getParent();
+ MachineInstr *Op1WideDef = MRI.getOneDef(Op1Wide)->getParent();
----------------
Any reason to not use `getVRegDef` here?
(I would recommend `getOpcodeDef`, but I think that walks past G_ASSERT_ZEXT)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D111888/new/
https://reviews.llvm.org/D111888
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