[PATCH] D112466: [NVPTX] Annotate LDG/LDU instructions as mayLoad

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic created this revision.
asavonic added reviewers: jlebar, jholewinski, tra.
Herald added a subscriber: hiraditya.
asavonic requested review of this revision.
Herald added subscribers: llvm-commits, jdoerfert.
Herald added a project: LLVM.

This patch fixes machine verifier errors:

      *** Bad machine code: Missing mayLoad flag ***
      - function:    foo1
      - basic block: %bb.0  (0x5560fc64ef08)
      - instruction: %4:float32regs =
  	INT_PTX_LDG_GLOBAL_f32areg64 killed %3:int64regs
  	:: (load (s32) from %ir.from1, addrspace 1)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112466

Files:
  llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
  llvm/test/CodeGen/NVPTX/bug26185-2.ll
  llvm/test/CodeGen/NVPTX/bug26185.ll
  llvm/test/CodeGen/NVPTX/ldg-invariant.ll
  llvm/test/CodeGen/NVPTX/ldu-i8.ll
  llvm/test/CodeGen/NVPTX/ldu-ldg.ll
  llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
  llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
  llvm/test/CodeGen/NVPTX/read-global-variable-constant.ll

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