[PATCH] D112342: [RISCV] Add vcsr CSR name for V extension.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 25 08:56:43 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG210b586a85be: [RISCV] Add vcsr CSR name for V extension. (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D112342/new/
https://reviews.llvm.org/D112342
Files:
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/test/MC/RISCV/rvv-user-csr-names.s
Index: llvm/test/MC/RISCV/rvv-user-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rvv-user-csr-names.s
+++ llvm/test/MC/RISCV/rvv-user-csr-names.s
@@ -56,6 +56,20 @@
# uimm12
csrrs t2, 0x00a, zero
+# vcsr
+# name
+# CHECK-INST: csrrs t1, vcsr, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x00]
+# CHECK-INST-ALIAS: csrr t1, vcsr
+# uimm12
+# CHECK-INST: csrrs t2, vcsr, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x00]
+# CHECK-INST-ALIAS: csrr t2, vcsr
+# name
+csrrs t1, vcsr, zero
+# uimm12
+csrrs t2, 0x00f, zero
+
# vl
# name
# CHECK-INST: csrrs t1, vl, zero
Index: llvm/lib/Target/RISCV/RISCVSystemOperands.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -385,6 +385,7 @@
def : SysReg<"vstart", 0x008>;
def : SysReg<"vxsat", 0x009>;
def : SysReg<"vxrm", 0x00A>;
+def : SysReg<"vcsr", 0x00F>;
def : SysReg<"vl", 0xC20>;
def : SysReg<"vtype", 0xC21>;
def : SysReg<"vlenb", 0xC22>;
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D112342.382018.patch
Type: text/x-patch
Size: 1083 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20211025/7113021f/attachment.bin>
More information about the llvm-commits
mailing list