[PATCH] D110231: [AMDGPU] Add constrained shift pattern matches.

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

LGTM, thanks!

Possible future improvement: apply this to other instructions like s_bfm and v_alignbit, which have an operand that works like a shift amount.



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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructions.td:249
+def cshl_#width : PatFrags<(ops node:$src0, node:$src1),
+  [(shl node:$src0, node:$src1), (shl node:$src0, (and node:$src1, mask))]>;
+defvar cshl = !cast<SDPatternOperator>("cshl_"#width);
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Possible future improvement: instead of ignoring AND with mask, ignore AND with any value that has all those bits set, but possibly more. For example you could ignore AND with 0xFF here. X86 isUnneededShiftMask does this.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110231/new/

https://reviews.llvm.org/D110231