[PATCH] D112320: [SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads

Mon Oct 25 06:33:22 PDT 2021

kmclaughlin added a comment.

In D112320#3080828 <https://reviews.llvm.org/D112320#3080828>, @CarolineConcatto wrote:

> Do we know what was the logic to set ExtType to  ISD::EXTLOAD?
> I don't see that on other parts of the legalisation for Masked load.

Hi @CarolineConcatto, thank you for taking a look at this. We are promoting the masked load by extending the return type, which is why we need to set ExtType when we create the new masked load with the promoted type. The original masked load which had an illegal return type may not have been extending, e.g.

  nxv2i16,ch = masked_load<(load (s32) from %ir.in, align 2)> t0, t2, undef:i64, t4, undef:nxv2i16
  ->
  nxv2i64,ch = masked_load<(load (s32) from %ir.in, align 2), anyext from nxv2i16> t0, t2, undef:i64, t4, undef:nxv2i64

================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:762
+
   SDLoc dl(N);
   SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
----------------
CarolineConcatto wrote:
> As we are replacing ExtType, do we need to pass isExpanding?
> I can see in void DAGTypeLegalizer::SplitVecRes_MLOAD and DAGTypeLegalizer::WidenVecRes_MLOAD 
> they have a 
> XLD->isExpandingLoad()
I think we should be passing isExpandingLoad here, I can see in PromoteIntOp_MSTORE we similarly pass N->isCompressingStore()

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