[PATCH] D111638: [AArch64][SVE] Combine predicated FMUL/FADD into FMA

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:769
+                            Options.UnsafeFPMath);
+  if(AllowFusionGlobally){
+    auto FMLA = instCombineSVEVectorFMLA(IC, II);
----------------
This logic needs tweaking; AllowFusionGlobally is independent of the fast math checks, so if either are present the optimization should take place.

Also would be good to see some tests covering these cases.


================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:771
+    auto FMLA = instCombineSVEVectorFMLA(IC, II);
+    if(FMLA)
+      return FMLA;
----------------
Looks as though clang format is needed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111638/new/

https://reviews.llvm.org/D111638