[PATCH] D111221: [AArch64][SVE] Improve code generation for VLS i1 masks

[Bradley Smith via Phabricator via llvm-commits]

bsmith added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:36
 #include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
----------------
Rogue include?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16047
+    auto OrigPred = LHS->getOperand(0)->getOperand(0)->getOperand(0);
+    if (Pred.getConstantOperandVal(0) == OrigPred.getConstantOperandVal(0))
+      return LHS->getOperand(0);
----------------
Is this assuming that Pred and OrigPred and ptrues? If they're not, won't this break?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111221/new/

https://reviews.llvm.org/D111221