[PATCH] D112429: [ARM] Implement PAC return address signing mechanism for PACBTI-M

Mon Oct 25 03:33:35 PDT 2021

stuij created this revision.
Herald added subscribers: rupprecht, hiraditya, kristof.beyls, emaste, dschuff.
Herald added a reviewer: jhenderson.
stuij requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.

This patch implements PAC return address signing for armv8-m. This patch roughly
accomplishes the following things:

- PAC and AUT instructions are generated.
- They're part of the stack frame setup, so that shrink-wrapping can move them

inwards to cover only part of a function

- The auth code generated by PAC is saved across subroutine calls so that AUT

can find it again to check

- PAC is emitted before stacking registers (so that the SP it signs is the one

on function entry).

- The new pseudo-register ra_auth_code is mentioned in the DWARF frame data
- With CMSE also in use: PAC is emitted before stacking FPCXTNS, and AUT

validates the corresponding value of SP

- Emit correct unwind information when PAC is replaced by PACBTI
- Handle tail calls correctly

Some notes:

We make the assembler accept the `.save {ra_auth_code}` directive that is
emitted by the compiler when it saves a register that contains a
return address authentication code.

For EHABI we need to have the `FrameSetup` flag on the instruction and
handle the `t2PACBTI` opcode (identically to `t2PAC`), so we can emit
`.save {ra_auth_code}`, instezd of `.save {r12}`.

For PACBTI-M, the instruction which computes return address PAC should use SP
value before adjustment for the argument registers save are (used for variadic
functions and when a parameter is is split between stack and register), but at
the same it should be after the instruction that saves FPCXT when compiling a
CMSE entry function.

This patch moves the varargs SP adjustment after the FPCXT save (they are never
enabled at the same time), so in a following patch handling of the `PAC`
instruction can be placed between them.

Epilogue emission code adjusted in a similar manner.

PACBTI-M code generation should not emit any instructions for architectures
v6-m, v8-m.base, and for A- and R-class cores. Diagnostic message for such cases
is handled separately by a future ticket.

note on tail calls:

If the called function has four arguments that occupy registers `r0`-`r3`, the
only option for holding the function pointer itself is `r12`, but this register
is used to keep the PAC during function/prologue epilogue and clobbers the
function pointer.

When we do the tail call we need the five registers (`r0`-`r3` and `r12`) to
keep six values - the four function arguments, the function pointer and the PAC,
which is obviously impossible.

One option would be to authenticate the return address before all callee-saved
registers are restored, so we have a scratch register to temporarily keep the
value of `r12`. The issue with this approach is that it violates a fundamental
invariant that PAC is computed using CFA as a modifier. It would also mean using
separate instructions to pop `lr` and the rest of the callee-saved registers,
which would offset the advantages of doing a tail call.

Instead, this patch disables indirect tail calls when the called function take
four or more arguments and the return address sign and authentication is enabled
for the caller function, conservatively assuming the caller function would spill
LR.

This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:

https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension

The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:

https://developer.arm.com/documentation/ddi0553/latest

The following people contributed to this patch:

- Momchil Velikov
- Ties Stuij

Change-Id: I66e6c79472a473e37bc54a595c644b237a427be4
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/c/armcompiler/llvm-project/+/286250
Reviewed-by: Mikhail Maltsev <mikhail.maltsev at arm.com>
Tested-by: sdct odin <sdct.odin at arm.com>

SDCOMP-57212: update encoding of the `pop ra_auth_code` instruction

Change-Id: I5533aa4f17dfac33b57db2d465442fa5a97fa26c
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/c/armcompiler/llvm-project/+/287396
Reviewed-by: Momchil Velikov <momchil.velikov at arm.com>
Tested-by: Ties Stuij <ties.stuij at arm.com>

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112429

Files:
  llvm/include/llvm/Support/ARMEHABI.h
  llvm/lib/Target/ARM/ARMAsmPrinter.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMBranchTargets.cpp
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
  llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
  llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
  llvm/test/CodeGen/ARM/ipra-reg-usage.ll
  llvm/test/CodeGen/ARM/machine-outliner-calls.mir
  llvm/test/CodeGen/ARM/machine-outliner-default.mir
  llvm/test/CodeGen/ARM/machine-outliner-lr-regsave.mir
  llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
  llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
  llvm/test/CodeGen/ARM/va_arg.ll
  llvm/test/CodeGen/ARM/vargs_align.ll
  llvm/test/CodeGen/Thumb2/bti-pac-replace-1.mir
  llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-indirect-tail-call.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-2.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-5.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-overalign.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-unsupported-arch.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-varargs-1.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-varargs-2.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll
  llvm/test/MC/ARM/ra-auth-code-errors.s
  llvm/test/MC/ARM/ra-auth-code.s
  llvm/test/MC/Disassembler/ARM/sub-sp-imm-thumb2.txt
  llvm/test/tools/llvm-readobj/ELF/ARM/unwind.s
  llvm/tools/llvm-readobj/ARMEHABIPrinter.h

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