[PATCH] D112395: [AMDGPU] Enable 48-bit mul in AMDGPUCodeGenPrepare.

[Abinav Puthan Purayil via Phabricator via llvm-commits]

abinavpp added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp:536
+    // mul48 (i.e. mul24, mul24hi pair) would truncate the result.
+    if (Size > 48 && LHSBits + RHSBits > 48)
       return false;
----------------
abinavpp wrote:
> abinavpp wrote:
> > I think we were incorrect in doing the `LHSBits + RHSBits > ...` check in D111523. We did not consider the case when an operand has > 24 known bits, but the sum of known bits being in limits. mul24 instruction works only on the low-order 24 bits of its operands.
> Ignore this comment. I missed the operand width check in the if above.
Just realized that this if and the similar one for signed below is not required.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112395/new/

https://reviews.llvm.org/D112395