[llvm] d34cad3 - [AMDGPU] add tests for alternate form of usubsat; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-10-24T07:52:07-04:00
New Revision: d34cad31963f4f2af5174879cb556146e06d46be

URL: https://github.com/llvm/llvm-project/commit/d34cad31963f4f2af5174879cb556146e06d46be
DIFF: https://github.com/llvm/llvm-project/commit/d34cad31963f4f2af5174879cb556146e06d46be.diff

LOG: [AMDGPU] add tests for alternate form of usubsat; NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/usubsat.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/usubsat.ll b/llvm/test/CodeGen/AMDGPU/usubsat.ll
index 322cf31bed2d1..8b3e60038543a 100644
--- a/llvm/test/CodeGen/AMDGPU/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/usubsat.ll
@@ -109,6 +109,86 @@ define i16 @usubsat_as_bithack_i16(i16 %x) {
   ret i16 %result
 }
 
+define i16 @usubsat_as_bithack2_i16(i16 %x) {
+; GFX6-LABEL: usubsat_as_bithack2_i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v1, v0, 0, 16
+; GFX6-NEXT:    v_ashrrev_i32_e32 v1, 15, v1
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, 0xffff8000, v0
+; GFX6-NEXT:    v_and_b32_e32 v0, v1, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: usubsat_as_bithack2_i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_ashrrev_i16_e32 v1, 15, v0
+; GFX8-NEXT:    v_add_u16_e32 v0, 0x8000, v0
+; GFX8-NEXT:    v_and_b32_e32 v0, v1, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: usubsat_as_bithack2_i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_ashrrev_i16_e32 v1, 15, v0
+; GFX9-NEXT:    v_add_u16_e32 v0, 0x8000, v0
+; GFX9-NEXT:    v_and_b32_e32 v0, v1, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: usubsat_as_bithack2_i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_ashrrev_i16 v1, 15, v0
+; GFX10-NEXT:    v_add_nc_u16 v0, 0x8000, v0
+; GFX10-NEXT:    v_and_b32_e32 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %signsplat = ashr i16 %x, 15
+  %flipsign = add i16 %x, 32768
+  %result = and i16 %signsplat, %flipsign
+  ret i16 %result
+}
+
+define i16 @usubsat_as_bithack_commute_i16(i16 %x) {
+; GFX6-LABEL: usubsat_as_bithack_commute_i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v1, v0, 0, 16
+; GFX6-NEXT:    v_ashrrev_i32_e32 v1, 15, v1
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, 0xffff8000, v0
+; GFX6-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: usubsat_as_bithack_commute_i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_ashrrev_i16_e32 v1, 15, v0
+; GFX8-NEXT:    v_add_u16_e32 v0, 0x8000, v0
+; GFX8-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: usubsat_as_bithack_commute_i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_ashrrev_i16_e32 v1, 15, v0
+; GFX9-NEXT:    v_add_u16_e32 v0, 0x8000, v0
+; GFX9-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: usubsat_as_bithack_commute_i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_ashrrev_i16 v1, 15, v0
+; GFX10-NEXT:    v_add_nc_u16 v0, 0x8000, v0
+; GFX10-NEXT:    v_and_b32_e32 v0, v0, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %signsplat = ashr i16 %x, 15
+  %flipsign = add i16 %x, 32768
+  %result = and i16 %flipsign, %signsplat
+  ret i16 %result
+}
+
 define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
 ; GFX6-LABEL: v_usubsat_i32:
 ; GFX6:       ; %bb.0: